New job Hiring Memory Layout Engineer For Bangalore,Having 3+ year Exp.

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Group: Current Openings Subject: Hiring Memory Layout Engineer For Bangalore,Having 3+ year Exp. Atul Prakash posted a job: Hiring Memory Layout Engineer For Bangalore,Having 3+ year Exp. "Candidate Should Have Understanding Of Different Memory Architectures,Memory Layout Tiling Methodology And Should Have Hands On Experience In Layout Design Of Memory Leaf Cells And At Top Level Of Memories In DSM Process Nodes And Have Understanding Of Issues Like WPE, LOD Effects.Must Have Good Understanding Of Physical Verification Checks – DRC, LVS, ERC And Reliability Checks – IR And EM. Must Have Worked On Cadence Tools For Layout Design And Cadence/Mentor/Synopsys Tools For Physical Verification Checks. He/She Must Have Good Understanding Of Basics Of CMOS Circuits.Basic Knowledge Of Skill Or Any Compiler Related Language Would Be Required.Send Your Resume At talent@yoctozant.com"

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