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Subject: Multiple openings for Layout Design(5-9yrs), System Verification(5+yrs), FPGA Design(5+yrs), Protocol Stack(<2 yrs) & Phy Design Manager(12+yrs). Loc: Bangalore. Apply @ http://embeddedcareers.com/

Arti Bhatia posted a job: Multiple openings for Layout Design(5-9yrs), System Verification(5+yrs), FPGA Design(5+yrs), Protocol Stack(<2 yrs) & Phy Design Manager(12+yrs). Loc: Bangalore. Apply @ http://embeddedcareers.com/

"http://embeddedcareers.com/ Invites candidatures for for Layout Design (5-9yrs), System Verification (5+yrs), FPGA Design (5+yrs), Protocol Stack Development (<2 yrs) & Physical Design Manager (12+yrs). A Brief of requirement is listed below. To Apply and for detailed JDs: get registered at embeddedcareers.com. Layout - Design Engineer. Experience: 5-9 years. Location: Bangalore Bachelor's/Master's in Electronics, Electrical Engineering. 5-9 years of experience in layout activities of complex SOC Knowledge of tools like Synopsys ICC, Primetime STA, Power analysis tools like primerail Layout and timing closure of digital macros and having worked on million gate design layout Usage of Synopsys ICC tools System Verification Engineers Experience: 5+ years Location: Bangalore E/BTech /or Masters in Engineering in Computer Science/Electronics academic records from good institutes, Experience on "OVM/UVM/VMM","System Verilog","Verification" Familiarity with protocols like PCIe,SGMII,SMII,I2C etc. FPGA Design Engineer. Experience: 5+ years Location: Bangalore Education: BE/BTech /or Masters in Engineering in Computer Science/Electronics academic records from good institutes, Experience for IP integration (gige, pcie, spi, i2c, ddr, flash, cpu local bus). FPGA/ASIC Design, pin-outs, clocking, digital logic , verilog coding, xilinx tools Protocol stacks development. Experience: 2years Location Bangalore BE/B.Tech/M.Tech/PhD protocol stack development, 3GPP specifications, LTE, UMTS Will be working on LTE Protocol Stack (NAS, RRC, RLC, MAC) in an embedded environment (ARM processor). Experience with lab equipment (R&S/Aeroflex/Anite Protocol Testers) is desirable Physical Design Manager (PHY Layer, DSP, SoCs, DSP). Experience: 12+ years Location: Bangalore Bachelors/Masters/PhD in Electrical / Electronic engineering with focus on Communication engineering from reputed institutes Product development experience in WiFi/WiMAX/LTE/3G/HSDPA/HSUPA Strong programming skills (C/Assembly), experience in programming complex multi-core multi-processor DSP based SoCs; experience in optimizing implementation of DSP algorithms Arti Bhatia Marketing Executive Embedded Careers http://embeddedcareers.com http://embeddedcareers.blogspot.com/. http://twitter.com/#!/CareersAtEC https://www.facebook.com/embeddedcareers https://plus.google.com/b/104052181480719774958/"

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