Saturday, May 26, 2012

New job Openings for Analog/ Mixed Signal Design, Place & Route (Lead), Manager – Verification Service Projects. Exp: 5-10 yrs. Locs: USA & India Apply @ http://embeddedcareers.com/index.php

LinkedIn Following

  • Group: JOBS 2.0: Job Search Career Networking Staffing. Post Resume -Get Paid by Employers at Resumark .com
  • Subject: Openings for Analog/ Mixed Signal Design, Place & Route (Lead), Manager – Verification Service Projects. Exp: 5-10 yrs. Locs: USA & India Apply @ http://embeddedcareers.com/index.php

Arti Bhatia posted a job: Openings for Analog/ Mixed Signal Design, Place & Route (Lead), Manager – Verification Service Projects. Exp: 5-10 yrs. Locs: USA & India Apply @ http://embeddedcareers.com/index.php

"1) Analog/Mixed-Signal Design Engineer (ADC, ADE). Exp: 5-10 years. Location California USA Analog/Mixed-Signal Design Engineer to join our team and work onsite at our customer’s location in near Thousand Oaks, California. The project duration is 3-6 months. Requirements: • Experience should include various Analog-to-Digital Converter (ADC) architecture designs. • At least 5-10 years of production design experience is required. • Cadence schematic capture, Analog Design Environment (ADE), and layout knowledge is required. • B.S. or higher in Electrical Engineering or equivalent degree. • Strong verbal communication skill. Desirable: • Experience with various ADC architectures is preferred. • Experience designing CMOS/CCD image sensors is highly desired. 2) Lead Place & Route Engineer for 40nm projects. Exp: 5-10 years. Location: California USA Specific tool experience required: • Magma - Talus, Tekton (STA), Synopsys - Formality • TCL and scripting Required skills (must haves): • P&R, STA , Formal Verification • IR/EM drop; power analysis Required skills (must haves): • P&R, STA , Formal Verification • IR/EM drop; power analysis Project Description: 1.) Large 50M gates device, including analog RF target to run at 15-20GHz 2.) Large 37M gates device, including 13 power islands, fast SerDes interfaces Duties and Responsibilities: • work on complex block P&R and/or top level P&R • assist leading and guiding block designers • analyze and propose solution to meet timing closure and schedule • assist in communicating with customer and manage expectations Required skills (must haves): • P&R, STA , Formal Verification • IR/EM drop; power analysis • Experience with advanced nodes (40nm and below) Specific tool experience required: • Magma - Talus, Tekton (STA), Synopsys - Formality • TCL and scripting • Synopsys Design Constraints. (SDC), DC & PrimeTime 3) Manager – Verification Service Projects. Exp: 5-7 years. Location Bangalore Education/Experience: 1. 5-7 years of good quality experience 2. B.Tech/M.Tech from top-tier engineering college 3. Prior experience in delivering design/verification services 4. Prior experience with USB/MIPI is a plus 5. No frequent job changes 6. Preference for small company environment Personal Characteristics: 1. Service mindset with maturity and self-confidence 2. Good communication skills 3. Detail oriented 4. Passionate about technology Skills Required: 1. SystemVerilog/C/Verilog based test-bench development 2. Expertise in at least one major verification methodology (OVM/VMM/UVM) 3. Micro-arch design/development experience is a plus 4. FPGA prototyping/Emulation experience is a plus To Apply and for detailed JDs: Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com. Arti Bhatia Marketing Executive Embedded Careers http://embeddedcareers.com http://embeddedcareers.blogspot.com/. http://twitter.com/#!/CareersAtEC https://www.facebook.com/embeddedcareers"

Don't want to get activity notifications: Change your following people settings »

Learn more about following people's activity

LinkedIn values your privacy. At no time has LinkedIn made your email address available to any other LinkedIn user without your permission. ©2012, LinkedIn Corporation.

No comments:

Earlier Posts