Thursday, August 8, 2013

New job Hiring Memory Modeling/QA engineer for Bangalore, having 3+ year of exp.

LinkedIn Following

  • Group: Current Openings
  • Subject: Hiring Memory Modeling/QA engineer for Bangalore, having 3+ year of exp.

Atul Prakash posted a job: Hiring Memory Modeling/QA engineer for Bangalore, having 3+ year of exp.

"The job involves Hardware modeling of memory blocks, writing memory simulation model in verilog/VHDL for DRAM, Flash, EEPROM etc memory, FE Synthesis & Timing Analysis, Memory DFT and BIST Desired Profile. A person Who can do Memory modeling & QA of front-end and back-end views. Experience in microarchitechture and RTL coding of IP blocks. Knowledge of memory modeling, bus architecture is required Expertise in Verilog and VHDL at RTL constructs level Tools used: NC Sim, NCVerilog, ModelSim. Knowledge of Tcl/Tk or any scripting language would be added advantage. Good communication skill set, good team play. send ur resume at talent@yoctozant.com"

Don't want to get activity notifications: Change your following people settings »

Learn more about following people's activity

 
This email was intended for Openings India (Owner, Recruitment India). Learn why we included this. © 2013, LinkedIn Corporation. 2029 Stierlin Ct. Mountain View, CA 94043, USA
 

No comments:

Earlier Posts